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| Author(s): |
Jose Arnaldo Mascagni de Holanda
Total Authors: 1
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| Document type: | Doctoral Thesis |
| Press: | São Carlos. |
| Institution: | Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB) |
| Defense date: | 2017-05-17 |
| Examining board members: |
Eduardo Marques;
Rodolfo Jardim de Azevedo;
Miguel Octavio Arias Estrada;
Emerson Carlos Pedrino;
Valentin Obac Roda
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| Advisor: | Eduardo Marques |
| Abstract | |
Among the several Advanced Driver Assistance (ADAS) technologies that have been added to modern vehicles are pedestrian detection systems. Those systems use sensors, such as radars, lasers, and video cameras to capture information from the environment and avoid collision with people in the context of traffic. Video cameras have become as a great option for such systems because of the relatively low cost and all of information they are able to capture from the environment. Many techniques for vison-based pedestrian detection have appeared in the last years, having as characteristic the necessity of a great computational power so that image can be processed in real time, in a robust and reliable way, and with low error rate. In addition, systems that implement these techniques require low power consumption, so they can operate in an embedded environment such as automobiles. A trend of these systems is the processing of images from multiple cameras mounted in vehicles, so that the system can detect potential collision hazards around the vehicle. In this context, this work addresses the hardware and software codesign of an architecture for pedestrian detection, considering the presence of four cameras in a vehicle (one in the front, one in the rear and two in the sides). For this purpose, the flexibility of FPGA devices is used for design space exploration and the construction of an architecture that provides the necessary performance, energy consumption at appropriate levels and also allows adaptation to new scenarios and evolution of pedestrian detection techniques through programmability. The development of the architecture was based on two algorithms widely used for pedestrian detection, which are Histogram of Oriented Gradients (HOG) and Integral Channel Features (ICF). Both introduce techniques that serve as the basis for modern detection algorithms. The implemented architecture allowed the exploration of different types of parallelism through the use of multiple softcore processors, as well as the acceleration of critical functions through implementations in hardware. It has also been demonstrated its feasibility in attending to a system containing four video cameras. (AU) | |