Methodology and design of a tool to co-simulate VHDL and SystemC

Author(s)

Richard Maciel Costa

• Document type: Master's Dissertation
• Press: Campinas, SP.
• Institution: Universidade Estadual de Campinas (UNICAMP). Instituto de Computação
• Defense date: 2008-08-15

Examining board members

Sandro Rigo; Roberto A Hexsel; Rodolfo Jardim de Azevedo

• Advisor: Guido Costa Souza de Araújo; Sandro Rigo

Abstract

In a recent past, systems were mostly constituted by well-separated parts such as microprocessors, memories and Application Specific Integrated Circuits (ASICs). That simple and clear organization allowed entire systems to be designed by only a few designers through a top-down approach: from the behavioral or register transfer model (using VHDL, for instance) advancing to the transistor-to-transistor level. However, the continuous advance of the process of shrinking transistors made it possible to create entire systems integrated in a single die (called System-on-chip). Because these systems are usually constituted by many complex components, a higher abstraction level - the system level - was created, together with the associated languages, to ease the work of the designers. The languages used to model on the system level are diferent from the languages used to model on the behavioral and register-transfer levels. Therefore, the problem of how to co-verify components written in diferent abstraction levels arises; this co-verification is desirable for big projects, since it provides a way to check if the components of the target system are working together. This project presents a methodology to solve the co-simulation problem between the hardware description language VHDL and the system description languagem SystemC through the use of the Verilog Procedural Interface (VPI). We describe the methodology and also describe the framework used to validate the methodology and comparative tests between this framework and a well-known comercial tool. (AU)