Design and analysis of evolutionary bit-length optimization algorithms for floating to fixed-point conversion

Author(s)

Rosa, L. S. ; Delbem, A. C. B. ; Toledo, C. F. M. ; Bonato, V.

• Document type: Journal article
• Source: APPLIED SOFT COMPUTING; v. 49, p. 447-461, DEC 2016.
• Web of Science Citations: 2

Abstract

Hardware designs need to obey constraints of resource utilization, minimum clock frequency, power consumption, computation precision and data range, which are all affected by the data type representation. Floating and fixed-point representations are the most common data types to work with real numbers where arithmetic hardware units for fixed-point format can improve performance and reduce energy consumption when compared to floating point solution. However, the right bit-lengths estimation for fixed-point is a time-consuming task since it is a combinatorial optimization problem of minimizing the accumulative arithmetic computation error. This work proposes two evolutionary approaches to accelerate the process of converting algorithms from floating to fixed-point format. The first is based on a classic evolutionary algorithm and the second one introduces a compact genetic algorithm, with theoretical evidence that a near-optimal performance, to find a solution, has been reached. To validate the proposed approaches, they are applied to three computing intensive algorithms from the mobile robotic scenario, where data error accumulated during execution is influenced by sensor noise and navigation environment characteristics. The proposed compact genetic algorithm accelerates the conversion process up to 10.2x against the state of art methods reaching similar bit precision and robustness. (C) 2016 Elsevier B.V. All rights reserved. (AU)

• FAPESP's process: 14/14918-2 - Code snippets identification for pipeline processing in FPGA accelerators for heterogeneous platforms
• Grantee: Leandro de Souza Rosa
• Support Opportunities: Scholarships in Brazil - Doctorate (Direct)