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(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation

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Nogueira, Gabriel Leonardo [1] ; Ozorio, Maiza da Silva [1] ; da Silva, Marcelo Marques [1] ; Morais, Rogerio Miranda [1] ; Alves, Neri [1]
Total Authors: 5
[1] Sao Paulo State Univ UNESP, Sch Technol & Appl Sci, BR-19060900 Presidente Prudente, SP - Brazil
Total Affiliations: 1
Document type: Journal article
Source: ELECTRONIC MATERIALS LETTERS; v. 14, n. 3, p. 319-327, MAY 2018.
Web of Science Citations: 0

We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3 covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3 surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, V-TH = - 8 V and E-TH = 354.5 MV/m respectively, were calculated using an Al2O3 film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3 these values were V-TH = - 10 V and E-TH = 500 MV/m. {[}GRAPHICS] . (AU)

FAPESP's process: 13/26973-5 - Preparation and characterization of an organic field effect transistor using a vertical architecture
Grantee:Gabriel Leonardo Nogueira
Support type: Scholarships in Brazil - Master
FAPESP's process: 14/13015-9 - Development of thin film transistors for printed inverter circuits on flexible substrates
Grantee:Neri Alves
Support type: Regular Research Grants