Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs

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Author(s):	Rodrigues, Jaime C. ; Mariniello, Genaro ; Casse, Mikael ; Barraud, Sylvain ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A. ; IEEE Total Authors: 8
Document type:	Journal article
Source:	35TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO2021); v. N/A, p. 4-pg., 2021-01-01.
Abstract
This paper aims at analyzing the electrical characteristics of 2-level Stacked Nanowire MOSFETs at low temperatures. Fundamental device parameters such as threshold voltage, subthreshold slope and transconductance are evaluated in the temperature range of 160K to 400K. The influence of fin width variation is also studied. An analytical model of multiple-gate nanowire MOSFETs is employed to explain the experimentally observed data. It is demonstrated that the threshold voltage increases linearly with the temperature reduction. Stacked nanowires with wider fin width presents larger threshold variation with temperature. (AU)

FAPESP's process:	19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
Grantee:	Marcelo Antonio Pavanello
Support Opportunities:	Regular Research Grants