Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Author(s)

Mariniello, Genaro ; Barraud, Sylvain ; Vinet, Maud ; Casse, Mikael ; Faynot, Olivier ; Calcade, Jaime ; Pavanello, Marcelo Antonio

• Document type: Journal article
• Source: Solid-State Electronics; v. 194, p. 7-pg., 2022-04-26.

Abstract

This paper aims at analyzing the electrical characteristics of n-type vertically stacked nanowires with variable fin width, operating in the temperature range of 300-600 K. Basic electrical parameters, such as threshold voltage, subthreshold slope, and carrier mobility are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation, to access some of device's analog figures of merit. Also, it has been analyzed the DIBL, GIDL, I-on, and I-off. currents. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants