Optimizing a Robust Miller OTA Implemented with Diamond Layout Style for MOSFETs By Using iMTGSPICE

Author(s)

Banin Junior, Jose Roberto ; de Lima Moreto, Rodrigo Alves ; da Silva, Gabriel Augusto ; Thomaz, Carlos Eduardo ; Gimenez, Salvador Pinillos ; IEEE

• Document type: Journal article
• Source: 34TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2021); v. N/A, p. 6-pg., 2021-01-01.

Abstract

This paper describes an innovative methodology to design and optimize robust analog Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) with Diamond layout style (hexagonal gate shape) for Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), focusing on reducing their die areas and improving their electrical performances. The Miller CMOS Operational Transconductance Amplifier (OTA) is used to validate this design and optimization approach by using a computational tool, which integrates the human intelligence (expertise of the designer) and the artificial intelligence (use an evolutionary optimization algorithm to search robust potential solutions quickly and accurately). The 180 nm CMOS ICs technology node was considered in this work. The Longitudinal Corner Effect (LCE) and Parallel Connections of MOSFETs with different channel Lengths Effect (PAMDLE) present in the Diamond MOSFET structure are analytically modeled to be simulated in the SPICE. In addition, the iMTGSPICE computation tool was improved with a new feature to automatically convert Conventional MOSFETs (CMs) into Diamond MOSFETs (DMs). The main results show that the Miller CMOS OTA implemented with DMs (alpha = 45 degrees) can reduce up to 43% of their die area, practically without impairing the design specifications and robustness (Corner and Monte Carlo Analyses) in comparison to the one implemented with CM counterparts. Furthermore, these results were obtained quickly, i.e., approximately 4 hours to obtain five different robust potential solutions available to the designer. (AU)

• FAPESP's process: 18/21341-4 - Prototype of interactive computational intelligence for the design and optimization of analog CMOS integrated circuits
• Grantee: Rodrigo Alves de Lima Moreto
• Support Opportunities: Research Grants - Innovative Research in Small Business - PIPE