| Full text | |
| Author(s): |
Bergamaschi, F. E.
;
Ribeiro, T. A.
;
Paz, B. C.
;
de Souza, M.
;
Barraud, S.
;
Casse, M.
;
Vinet, M.
;
Faynot, O.
;
Pavanello, M. A.
Total Authors: 9
|
| Document type: | Journal article |
| Source: | IEEE TRANSACTIONS ON ELECTRON DEVICES; v. 69, n. 7, p. 7-pg., 2022-07-01. |
| Abstract | |
This work investigates the carrier mobility variation in Omega-gate silicon-on-insulator (SOI) nanowire MOS transistors induced by substrate (or back) biasing. The analysis is carried out through experimental measurements and 3-D TCAD simulation, performed in n-type devices with variable fin width. Mobility enhancement is observed for lower back bias levels, due to the initial conduction through the Si-BOX interface, which presents higher mobility, prior to the activation of the front channel. As back bias is increased, however, the strong substrate-induced electric field in the back channel (BC) is responsible for worsening scattering mechanisms in the BC, such as surface roughness and acoustic phonon scattering, inducing mobility degradation. The effect is amplified as the fin width increases. For short-channel devices, the use of back bias was more beneficial for mobility due to a stronger mobility enhancement and lower mobility degradation. (AU) | |
| FAPESP's process: | 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties |
| Grantee: | Marcelo Antonio Pavanello |
| Support Opportunities: | Regular Research Grants |