Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Author(s)

de Souza, Michelly ; Cerdeira, Antonio ; Estrada, Magali ; Casse, Mikael ; Barraud, Sylvain ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A.

• Document type: Journal article
• Source: Solid-State Electronics; v. 208, p. 4-pg., 2023-10-01.

Abstract

This paper presents an experimental assessment of gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors for different temperatures of operation, in the temperature range between 300 K and 580 K. The temperature rise increases the GIDL current and its dependence on the device width due to the increase of band-to-band generation with temperature and weakening of electrostatic coupling. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants
• FAPESP's process: 23/03006-1 - EUROSOI-ULIS 2023 - Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
• Grantee: Michelly de Souza
• Support Opportunities: Research Grants - Meeting - Abroad