Analysis of Bulk and Accumulation Mobilities in n- and p-type Triple Gate Junctionless Nanowire Transistors

Author(s)

Ribeiro, T. A. ; Pavanello, M. A. ; Cerdeira, A. ; IEEE

• Document type: Journal article
• Source: 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS; v. N/A, p. 4-pg., 2017-01-01.

Abstract

This paper studies the effective mobility in n- and p-type junctionless nanowire transistors (JNT) with variable fin width from quasi-planar to nanowire devices. JNTs electrical parameters were analyzed and the results show that smaller fin width have higher mobility while the mobility decreases for quasi-planar devices. Simulations were used to analyze the mobility showing that small fin devices reach higher mobility for smaller gate bias variation above the threshold voltage and a higher mobility in the middle of the channel due to the better electrostatic coupling compared to larger devices. (AU)

• FAPESP's process: 16/10832-1 - Evaluation and Modeling of Charge Transport in Nanometer MOSFETs for CMOS Circuit Design
• Grantee: Thales Augusto Ribeiro
• Support Opportunities: Scholarships in Brazil - Doctorate