Evaluation and Modeling of Charge Transport in Nanometer MOSFETs for CMOS Circuit Design

• Grant number: 16/10832-1
• Support Opportunities: Scholarships in Brazil - Doctorate
• Start date: October 01, 2016
• End date: May 31, 2020
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Thales Augusto Ribeiro
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil

Abstract

Multiple gate MOS transistors are a promising alternative to solve the problems arising from the continued reduction of the device dimensions, due to the improvements in the performance of MOS devices with extremely submicron dimensions (deep-submicrometer), with channel lengths smaller than 14 nm, because of the excellent control of channel charges.The double or triple gate transistors, such as FinFETs or with surrounding channel, are examples of structures that have been considered by the scientific community. Recently, a new transistor structure with multiple gates was proposed, the MOS transistor without junctions (junctionless). In this transistor channel, source and drain regions are made from the same type of dopant, avoiding the PN junctions. Juntionless devices demonstrated improvements to be applied in both digital and analog applications in comparison to standard MOSFETs with multiple gates and similar dimensions (with junctions). In addition to the absence of juctions, the charge transport in these transistors occurs in a completely different way than occurs in traditional MOS transistors. The junctionless devices have carriers transport based on accumulation regime in the channel region, while transistors with junctions are based on inversion phenomenon.Because of this change in physics governing the transport of charges in junctionless transistors, few studies can be found in the current literature regarding the carrier transport properties in these advanced structures. However, these few publications still present preliminary findings on the subject and they all perform technical adptions on methods applied to traditional transistors as a way to get information about the charge transportation of transistors without junctions. Detailed knowledge and subsequent modeling of physical phenomena governing the charge transport in junctionless transistors is critical because it directly impacts the electrical current and thus the performance of these devices in electrical circuits.In this research project will be carried out a comparative study of charge transportation in traditional transistors and junctionless, both structures with multiple doors and nanometric dimensions. It is expected to get a new model for the mobility of carriers in the channel region of the junctionless MOS transistors, which consider the peculiarities of operation of these structures to be included in electrical circuit simulators.

Scientific publications

(8)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

AUGUSTO RIBEIRO, THALES; CERDEIRA, ANTONIO; ESTRADA, MAGALI; BARRAUD, SYLVAIN; ANTONIO PAVANELLO, MARCELO. Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors. JOURNAL OF COMPUTATIONAL ELECTRONICS, v. 21, n. 3, p. 12-pg., 2022-04-02. (16/10832-1, 19/15500-5)

RIBEIRO, THALES AUGUSTO; BERGAMASCHI, FLAVIO ENRICO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures. Solid-State Electronics, v. 185, NOV 2021. (16/10832-1, 19/15500-5)

RIBEIRO, T. A.; PAVANELLO, M. A.; CERDEIRA, A.; IEEE. Analysis of Bulk and Accumulation Mobilities in n- and p-type Triple Gate Junctionless Nanowire Transistors. 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS, v. N/A, p. 4-pg., 2017-01-01. (16/10832-1)

RIBEIRO, T. A.; PAVANELLO, M. A.; IEEE. Analysis of the Electrical Parameters in SOI n-type Junctionless Nanowire Transistors at High Temperatures. LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC 2020), v. N/A, p. 4-pg., 2020-01-01. (16/10832-1)

RIBEIRO, THALES AUGUSTO; BARRAUD, SYLVAIN; BERGAMASCHI, FLAVIO ENRICO; PAVANELLO, MARCELO ANTONIO; IEEE. Influence of Fin Width Variation on the Electrical Characteristics of n-Type Junctionless Nanowire Transistors at High Temperatures. 2020 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., 2020-01-01. (16/10832-1, 19/15500-5)

RIBEIRO, THALES AUGUSTO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v. 9, p. 492-499, 2021. (16/10832-1, 19/15500-5)

RIBEIRO, T. A.; PAVANELLO, M. A.; IEEE. Analysis of the Scattering Mechanisms in the Accumulation Layer of Junctionless Nanowire Transistors at High Temperature. 2019 34TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO 2019), v. N/A, p. 4-pg., 2019-01-01. (16/10832-1)

PAVANELLO, MARCELO A.; RIBEIRO, THALES A.; CERDEIRA, ANTONIO; AVILA-HERRERA, FERNANDO; IEEE. Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors. 2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., 2021-01-01. (19/15500-5, 16/10832-1)