Modeling, electrical characterization and electrical parameter extraction of junctionless MOS transistors

• Grant number: 14/13816-1
• Support Opportunities: Scholarships abroad - Research Internship - Master's degree
• Start date: September 29, 2014
• End date: March 28, 2015
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Bruna Cardoso Paz
• Supervisor: Olivier Faynot
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil
• Institution abroad: Commissariat à l'énergie atomique et aux énergies alternatives (CEA), France
• Associated to the scholarship: 12/24377-3 - Modeling of Junctionless Nanowire MOS Transistors with Double and Triple Gate, BP.MS

Abstract

This project aims to sustain an international cooperation between the research group coordinated by Prof. Dr. Marcelo Antonio Pavanello, from Department of Electrical Engineering of Centro Universitário da FEI, situated in São Bernardo do Campo, Brazil, and the research group coordinated by Dr. Olivier Faynot, from the Laboratoire d'électronique et de technologie de l'information (Leti), situated in Grenoble, France. The Leti is one of the few research centers in the world capable of fabricating nanometer size junctionless devices. The main focus of the project will be the modelling, electrical characterization and parameter extraction of junctionless MOS Transistors. The project will be conducted by Mrs. Bruna Paz as a part of her M. Sc. thesis at FEI, in a stay of 6 months at Leti. During her stay Mrs. Paz will work to evolve the analytical model for double-gate junctionless MOSFETs to triple-gate ones. Also she will work on the electrical characterization of advanced short-channel junctionless devices fabricated at Leti and in their electrical parameter extraction intended to complete the ongoing model development.The stay at Leti will be of main interest in her M. Sc. work as she will be able to experimentally prove the validity of the model for short-channel junctionless devices with nanometer size. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

PAZ, B. C.; CASSE, M.; BARRAUD, S.; REIMBOLD, G.; FAYNOT, O.; AVILA-HERRERA, F.; CERDEIRA, A.; PAVANELLO, M. A.. Drain current model for short-channel triple gate junctionless nanowire transistors. MICROELECTRONICS RELIABILITY, v. 63, p. 1-10, AUG 2016. (14/13816-1, 12/24377-3)