Channel Width Influence on the Analog Performance of the Asymmetric Self-Cascode FD SOI nMOSFETs

Author(s)

Assalti, R. ; de Souza, M. ; Flandre, D. ; IEEE

• Document type: Journal article
• Source: 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS; v. N/A, p. 4-pg., 2017-01-01.

Abstract

In this paper, the analog performance of the Asymmetric Self-Cascode structure of Fully Depleted SOI nMOSFETs has been evaluated with regards to the variation of channel width, through three-dimensional numerical simulations. The largest gain has been obtained using the narrowest transistor near the source and the widest transistor near the drain. (AU)

• FAPESP's process: 15/08616-6 - Modeling, Simulation and Fabrication of Analog Circuits with Asymmetric Self-Cascode SOI Transistors
• Grantee: Rafael Assalti
• Support Opportunities: Scholarships in Brazil - Doctorate