| Grant number: | 13/22594-0 |
| Support Opportunities: | Scholarships in Brazil - Doctorate |
| Start date: | March 01, 2014 |
| End date: | November 30, 2017 |
| Field of knowledge: | Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation |
| Principal Investigator: | Paula Ghedini Der Agopian |
| Grantee: | Caio Cesar Mendes Bordallo |
| Host Institution: | Escola Politécnica (EP). Universidade de São Paulo (USP). São Paulo , SP, Brazil |
| Associated scholarship(s): | 15/09352-2 - Impact of III-V materials on tunneling field effect transistor (TFET) operating at different temperatures, BE.EP.DR |
Abstract With the continuous devices scaling, the fabrication CMOS technology, that actually is reaching nanometer scales, it has encountered some problems as the short channel effects. As an alternative for this technology, industries have changed the conventional CMOS technology by the silicon-on-insulator (SOI) technology. However, for dimensions below 22nm this technology has also been shown to have reached its scaling limit. Due to this scaling limit, new technologies have been studied to replace the MOS technology. Among these alternatives can be cited the tunneling induced field effect transistor (TFET), that is a device based on silicon and compatible with the CMOS technology, but with different operating principle. In these devices the current is composed by the tunneling of the carriers between bands, which makes possible a significant reduction of the off-state current (IOFF) and also allows sub threshold swing below the theoretical limit (60mV/dec) at room temperature. This work focus on the study of this new structure called tunneling field effect transistor (TFET), with nanometric dimensions, what have been one of the pointed alternatives by the scientific community as promising for the replacement of MOS devices due to its switch speed potential. However, this structure is very recent and needs to be widely studied. The performance of this new device will be studied considering different fabrication structures (FinFETs and Nanowires), different materials (Si, Si(1-X)Ge(X) and Ge) and for different operation temperatures. (AU) | |
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