Electrical characterization and tridimensional simulation of nanowires MOS transistors

• Grant number: 15/10491-7
• Support Opportunities: Scholarships in Brazil - Doctorate
• Start date: December 01, 2015
• End date: May 31, 2018
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Bruna Cardoso Paz
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil
• Associated scholarship(s): 16/06301-0 - Electrical characterization and tridimensional simulation of nanowires MOS transistors, BE.EP.DR

Abstract

The scaling of electronic devices has brought difficulties on using planar MOS transistors in extremely sub micrometric technologies due to the presence of short channel effects. Multiple gate MOS transistors increase significantly the gate control over the charges in the channel, reducing the occurrence of these effects. This is why these devices have shown to be of great interest for future technologies.Different multiple gate transistors such as double and triple gate FinFETs have earned attention in the scientific community due to their good behavior on digital applications. Recently developed, nanowire MOS transistors are another multiple gate structure that has shown promising results. These structures have a cross section of few nanometers, allowing excellent electrostatic control and reducing undesirable effects observed in MOS transistors with channel length as short as 10 nanometers.This research project aims to study the effect of temperature over electrical parameters of nanowires transistors, through numerical simulations and experimental measurements, in order to correlate the behavior of the devices with their physics. This analysis will be performed considering unstrained and strained silicon devices and different channel orientations. To reach the goals proposed in this work, tridimensional numerical simulations will be performed in short channel nanowires transistors as a function of temperature. The nanowires transistors that will be studied have been and will be fabricated a CEA-Leti, France. (AU)

Scientific publications

(16)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

CERDEIRA, A.; ESTRADA, M.; PAVANELLO, M. A.. On the compact modelling of Si nanowire and Si nanosheet MOSFETs. Semiconductor Science and Technology, v. 37, n. 2, FEB 1 2022. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Electrical characterization of vertically stacked p-FET SOI nanowires. Solid-State Electronics, v. 141, p. 84-91, MAR 2018. (15/10491-7, 16/06301-0)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO; IEEE. Back bias impact on effective mobility of p-type nanowire SOI MOSFETs. 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2018-01-01. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. Solid-State Electronics, v. 128, p. 7-pg., 2017-02-01. (15/10491-7)

PAZ, BRUNA CARDOSO; PAVANELLO, MARCELO ANTONIO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; SARAFIS, P; NASSIOPOULOU, AG. Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires. 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017), v. N/A, p. 4-pg., 2017-01-01. (15/10491-7, 16/06301-0)

MOLTO, ALLAN ROBERTO; PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO; IEEE. Low-Frequency Noise Investigation in Long-Channel Fully Depleted Inversion Mode n-type SOI Nanowire. 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2018-01-01. (15/10491-7)

BERGAMASCHI, FLAVIO ENRICO; BARRAUD, SYLVAIN; CASSE, MIKAEL; VINET, MAUD; FAYNOT, OLIVIER; PAZ, BRUNA CARDOSO; PAVANELLOA, MARCELO ANTONIO; IEEE. Impact of substrate bias on the mobility of n-type Omega-gate SOI nanowire MOSFETs. 2019 34TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO 2019), v. N/A, p. 4-pg., 2019-01-01. (15/10491-7)

PAZ, BRUNA CARDOSO; PAVANELLO, MARCELO ANTONIO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; GAMIZ, F; SVERDLOV, V; SAMPEDRO, C; et al. Cryogenic Operation of Omega-Gate p-type SiGe-on-Insulator Nanowire MOSFETs. 2018 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., 2018-01-01. (15/10491-7)

PAZ, BRUNA CARDOSO; DORIA, RODRIGO TREVISOLI; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO; IEEE. Non-linearity Analysis of Triple Gate SOI Nanowires MOSFETS. 2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2016-01-01. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Study of silicon n- and p-FET SOI nanowires concerning analog performance down to 100 K. Solid-State Electronics, v. 128, n. SI, p. 60-66, FEB 2017. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Low temperature influence on performance and transport of Omega-gate p-type SiGe-on-insulator nanowire MOSFETs. Solid-State Electronics, v. 159, n. SI, p. 83-89, SEP 2019. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs. Solid-State Electronics, v. 149, p. 62-70, NOV 2018. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs. Solid-State Electronics, v. 159, p. 7-pg., 2019-09-01. (15/10491-7)

MOLTO, ALLAN ROBERTO; PAZ, BRUNA CARDOSO; PAVANELLO, MARCELO ANTONIO; IEEE. Influence of fin width and back bias on the low-frequency noise of long channel SOI nanowires. 2019 LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., 2019-01-01. (15/10491-7)

BERGAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; DE SOUZA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A.; IEEE. Carrier Mobility Variation Induced by the Substrate Bias in Omega-gate SOI Nanowire MOSFETs. 2019 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2019-01-01. (15/10491-7)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO; IEEE. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2017-01-01. (15/10491-7, 16/06301-0)