Analog operation of multiple gate transistors as a function of the temperature.

Author(s)

Rodrigo Trevisoli Doria

• Document type: Doctoral Thesis
• Press: São Paulo.
• Institution: Universidade de São Paulo (USP). Escola Politécnica (EP/BC)
• Defense date: 2010-10-28

Examining board members

Marcelo Antonio Pavanello; José Alexandre Diniz; Mauricio Massazumi Oka; Sebastião Gomes dos Santos Filho; Gilson Inácio Wirth

• Advisor: Marcelo Antonio Pavanello

Abstract

In this work it is presented an analysis of the analog operation of multiple gate transistors, evaluating the Early Voltage, the open-loop voltage gain, the transconductance over the drain current ratio (gm/IDS), the drain conductance and, especially, the harmonic distortion exhibited by these devices. Along the work, FinFETs, Gate-All-Around (GAA) devices with the Graded-Channel (GC) structure and MOS transistors without junctions (Junctionless - JL) were studied. Initially, an analysis of the harmonic distortion presented by conventional and biaxially strained FinFETs with several fin widths (Wfin) and channel lengths (L) was performed, when these devices were operating in saturation as single transistor amplifiers. In this analysis, the non-linearities were evaluated through the extraction of the second and the third order harmonic distortions (HD2 and HD3, respectively), and it was shown that the presence of strain has negligible influence in HD2, but slightly changes HD3. When the open loop voltage gain of the devices is taken into consideration, narrower conventional transistors present a huge advantage with respect to the strained ones in terms of HD2. Also, it was perceived that both HD2 and HD3 of strained FinFETs worsen with the temperature decrease, especially in stronger inversion. In the sequence, an analysis of the HD3 presented by conventional and strained FinFETs of several fin widths and channel lengths operating in the triode regime was performed. These devices were applied to 2-MOS balanced structures, showing that the presence of the strain does not influence significantly the HD3, but reduces the resistance in the channel of the transistors (RON), which is not good for resistive structures as the ones evaluated. In this analysis, it can also be observed an HD3 improvement of 30 dB when VGT is increased from zero up to 1,0 V, where narrower devices present transfer characteristics more linear than the wider ones. Then, it was studied the distortion presented by GAA and GC GAA devices operating in the triode regime, applied to 2-MOS structures. In this case, it could be perceived that GC GAAs with longer lightly doped regions present better HD3 in comparison to the other devices for VGT higher than 2.0 V. In the evaluation of these structures as a function of the temperature, it could be seen that for VGT higher than 1.1 V, HD3 strongly depends on the temperature and worsens as the temperature decreases. The study involving JL transistors was focused on their analog parameters, comparing them to the ones presented by triple gate devices or FinFETs. In moderate and strong inversions, Junctionless showed lower values for gm/IDS with respect to triple gate devices biased at a similar current level. However, the dependence of gm/IDS from Junctionless with the temperature was also smaller than the one presented by FinFETs. Junctionless and FinFETs exhibited distinct behaviors for the Early voltage and the open-loop voltage gain as a function of the temperature. These parameters always improve with the temperature raise in JL devices whereas they exhibit their maximum values around room temperatures for FinFETs. In the proximity of the threshold voltage, Junctionless with fin width of 30 nm presented Early voltage and intrinsic gain larger than 80 V and 57 dB, respectively, whereas FinFETs exhibited Early voltage of 35 V and gain of 50 dB. For all the studies performed in this work, the probable causes of the non-linearities were pointed out, from analytic models that could correlate the physical work of the devices with the experimental results. (AU)

• FAPESP's process: 07/04439-6 - Analog operation of multiple gate transistors in cryogenic environments
• Grantee: Rodrigo Trevisoli Doria
• Support Opportunities: Scholarships in Brazil - Doctorate