| Full text | |
| Author(s): |
Bergamaschi, F. E.
;
Pavanello, M. A.
Total Authors: 2
|
| Document type: | Journal article |
| Source: | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY; v. 10, p. 7-pg., 2022-01-01. |
| Abstract | |
This work presents an analysis of the application of active substrate bias (or back bias) on the charge transport properties of n-type Omega-gate SOI nanowire MOS transistors with thin buried oxide (BOX) and variable fin width. Additionally, the influence of back bias on the electrical parameters of these devices is also investigated through DC parameters such as on-to-off-state current ratio and DIBL. The evaluation is conducted by 3D TCAD simulations calibrated with experimental data. The application of negative back bias on nMOS transistors not only shifts the threshold voltage, but also causes mobility degradation due to the negative potential on the channel pushing the charges against the gate oxide interface. On the other hand, when positive back bias is applied, despite the mobility improvement allowed by the back channel's superior mobility and the front channel's less compacted inversion layer, at higher substrate bias levels, a strong mobility degradation is observed in the back channel due to the substrate's high electric field, resulting in reduction of the channel's overall effective mobility. The application of positive substrate bias degrades the subthreshold slope, leading to smaller on-to-off-state current ratio, as well as the reduced control of channel charges by the gate electrode worsens the DIBL. (AU) | |
| FAPESP's process: | 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties |
| Grantee: | Marcelo Antonio Pavanello |
| Support Opportunities: | Regular Research Grants |