| Full text | |
| Author(s): |
Cerdeira, Antonio
;
Estrada, Magali
;
Mariniello Da Silva, Genaro
;
Calcade Rodrigues, Jaime
;
Pavanello, Marcelo A.
;
IEEE
Total Authors: 6
|
| Document type: | Journal article |
| Source: | 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2022-01-01. |
| Abstract | |
In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data. (AU) | |
| FAPESP's process: | 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties |
| Grantee: | Marcelo Antonio Pavanello |
| Support Opportunities: | Regular Research Grants |