Variability Modeling in Triple-Gate Junctionless Nanowire Transistors

Author(s)

Trevisoli, Renan ; Pavanello, Marcelo A. ; Doria, Rodrigo T. ; Capovilla, Carlos E. ; Barraud, Sylvain ; de Souza, Michelly

• Document type: Journal article
• Source: IEEE TRANSACTIONS ON ELECTRON DEVICES; v. 69, n. 8, p. 7-pg., 2022-08-01.

Abstract

This work aims at proposing an analytical model for the variability of the threshold voltage and drain current in junctionless nanowire transistors. The model is continuous in all operation regions and has been validated through Monte Carlo simulations using a physically based drain current model and 3-D numerical simulations. A discussion about the influences of each variability source based on the proposed model is carried out. Finally, the modeled results are compared to the experimental data for a fully physical validation. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants