Accounting for Series Resistance in the Compact Model of Triple-Gate Junctionless Nanowire Transistors

Advanced search

Search - Use quotation marks to get a more specific result

Index

Field of knowledge

Start date

Betweenand

Author(s):	Trevisoli, Renan ; Doria, Rodrigo T. ; de Souza, Michelly ; Pavanello, Marcelo A. ; IEEE Total Authors: 5
Document type:	Journal article
Source:	2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO); v. N/A, p. 4-pg., 2018-01-01.
Abstract
The aim of this work is to propose a method to account for the series resistance effect on the compact drain current model of Junctionless Nanowire Transistors. The model is validated through comparisons against iterative analysis and three-dimensional numerical simulations. The characteristics of the devices, i.e. the width, height, channel length, doping concentration and gate oxide thickness, have been varied in the analysis to demonstrate the model applicability. (AU)

FAPESP's process:	14/18041-8 - Electrical characterization and modeling of advanced electronic devices
Grantee:	Renan Trevisoli Doria
Support Opportunities:	Scholarships in Brazil - Post-Doctoral