Analog Performance of Self-Cascode SOI Nanowires nMOSFETs Aiming at Low-Power Applications

Author(s)

Assalti, R. ; de Souza, M. ; Casse, M. ; Barraud, S. ; Reimbold, G. ; Vinet, M. ; Faynot, O. ; IEEE

• Document type: Journal article
• Source: 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2017-01-01.

Abstract

This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages. (AU)

• FAPESP's process: 15/08616-6 - Modeling, Simulation and Fabrication of Analog Circuits with Asymmetric Self-Cascode SOI Transistors
• Grantee: Rafael Assalti
• Support Opportunities: Scholarships in Brazil - Doctorate