| Full text | |
| Author(s): |
Bergamaschi, F. E.
;
Ribeiro, T. A.
;
Paz, B. C.
;
de Souza, M.
;
Barraud, S.
;
Casse, M.
;
Vinet, M.
;
Faynot, O.
;
Pavanello, M. A.
;
IEEE
Total Authors: 10
|
| Document type: | Journal article |
| Source: | 2019 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2019-01-01. |
| Abstract | |
In this work, an experimental analysis on the carrier mobility of p- and n-type Omega-gate SOI nanowire MOS transistors with different fin widths is done by varying substrate bias. Y-function method was used to extract mobility and its degradation coefficients. Differently from previously reported data from pMOS transistors, in which carrier mobility degrades with substrate bias increase, an improvement in carrier mobility is verified for n-type devices when back bias is increased from negative voltages up to 10V. However, by raising back bias up to 100V, causes carrier mobility degradation. Three-dimensional simulations confirmed this effect and showed that strong back bias attract the channel to the bottom interface, causing carrier confinement and, thus, increasing scattering mechanisms. (AU) | |
| FAPESP's process: | 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors |
| Grantee: | Bruna Cardoso Paz |
| Support Opportunities: | Scholarships in Brazil - Doctorate |