Modeling the Interface Trap Density Influence on Junctionless Nanowire Transistors Behavior

Author(s)

Trevisoli, R. ; Doria, R. T. ; de Souza, M. ; Pavanello, M. A. ; IEEE

• Document type: Journal article
• Source: 2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2018-01-01.

Abstract

This work proposes a methodology for the modeling of the interface traps influence on the electrical characteristics of Junctionless Nanowire Transistors. The interface traps can influence the electrical behavior of junctionless in both on- and off-states due to the partial depletion regime operation, in which the surface potential varies with the applied biases. The methodology validation is performed using numerical simulations, where the drain current, the transconductance, the threshold voltage and the subthreshold slope have been analyzed. The modeling considering different traps energetic distributions has been demonstrated. (AU)

• FAPESP's process: 14/18041-8 - Electrical characterization and modeling of advanced electronic devices
• Grantee: Renan Trevisoli Doria
• Support Opportunities: Scholarships in Brazil - Post-Doctoral