| Full text | |
| Author(s): |
Mariniello, Genaro
;
Barraud, Sylvain
;
Vinet, Maud
;
Faynot, Olivier
;
Paz, Bruna Cardoso
;
Pavanello, Marcelo Antonio
;
IEEE
Total Authors: 7
|
| Document type: | Journal article |
| Source: | 2020 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS); v. N/A, p. 4-pg., 2020-01-01. |
| Abstract | |
This paper aims at analyzing the analog characteristics of n-type vertically stacked nanowires with 2 channels, varying the fin width and channel length. The basic electrical parameters such as threshold voltage and subthreshold slope are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation. (AU) | |
| FAPESP's process: | 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties |
| Grantee: | Marcelo Antonio Pavanello |
| Support Opportunities: | Regular Research Grants |