| Author(s): |
Costa, Fernando J.
;
Trevisoli, Renan
;
de Souza, Michelly
;
Doria, Rodrigo T.
;
IEEE
Total Authors: 5
|
| Document type: | Journal article |
| Source: | LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC 2020); v. N/A, p. 4-pg., 2020-01-01. |
| Abstract | |
The focus of this work is to perform an analysis of the thermal properties of the Self-Cascode (SC) structure composed by advanced UTBB SOI MOSFETs under a selected set of back gate biases, through 2D numerical simulations. In this work, it could be observed that the SC structure presents a 50 % lower thermal resistance in comparison with a single device with similar channel length. The application of a back gate bias of 2 V to the drainsided device or -2 V to the source-sided devices of the SC has shown a decrease of 10-16 % in the thermal resistance. (AU) | |
| FAPESP's process: | 14/18041-8 - Electrical characterization and modeling of advanced electronic devices |
| Grantee: | Renan Trevisoli Doria |
| Support Opportunities: | Scholarships in Brazil - Post-Doctoral |