Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors

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Author(s):	Pavanello, Marcelo A. ; Ribeiro, Thales A. ; Cerdeira, Antonio ; Avila-Herrera, Fernando ; IEEE Total Authors: 5
Document type:	Journal article
Source:	2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC); v. N/A, p. 4-pg., 2021-01-01.
Abstract
This paper presents the proposal of a compact analytical model for the transcapacitances of long-channel triple gate junctionless nanowire transistors. The model is validated using comparisons against 3D TCAD simulations showing very good agreement, with continuous transitions between all regions of operation. (AU)

FAPESP's process:	19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
Grantee:	Marcelo Antonio Pavanello
Support Opportunities:	Regular Research Grants


FAPESP's process:	16/10832-1 - Evaluation and Modeling of Charge Transport in Nanometer MOSFETs for CMOS Circuit Design
Grantee:	Thales Augusto Ribeiro
Support Opportunities:	Scholarships in Brazil - Doctorate