| Full text | |
| Author(s): |
Gimenez, Salvador Pinillos
;
Correia, Marcello Marcelino
Total Authors: 2
|
| Document type: | Journal article |
| Source: | Solid-State Electronics; v. 225, p. 8-pg., 2025-01-24. |
| Abstract | |
This work proposes a simple change of the channel CMOS ICs manufacturing processes to implement FinFETs, focusing on boosting their capacity to drive electrical drain current (IDS) concerning the Complementary Metal- Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) manufacturing process. Called "Gate-in-Diagonal Fin Field Effect Transistor (GiD-FinFET)", it was carefully designed to ensure its gate region is non-orthogonal to the Fin, as is observed in the standard Fin Field Effect Transistor (FinFET) counterpart. Three-dimensional (3D) numerical simulations were done using the Atlas Semiconductor Devices Simulator from Silvaco Co. to quantify the influence of the angle between the gate and Fin regions ((3) in the drain to source current, compared to the one observed in the conventional FinFET counterpart, considering that these devices present the same Fin volumes. The main results found show that the GiD-FinFETs I DS with a (3 equal to 45 degrees are 32 % (Triode Region: for V GS = 1.0 V and V DS equal to 0.5 V) and 33 % (Saturation Region: V GS equal to 1.2 V and V DS equal to 1.5 V), respectively, higher than those observed in the conventional FinFET counterpart. This can be justified mainly because the effective channel width of the GiD-FinFETs is 41.5 % larger than that observed in the traditional FinFET counterpart, which leads to better use of its Fin region for the conducting I DS concerning the one measured in the conventional FinFET. Therefore, based on these results, by changing the (3 between the gate and Fin regions, we can boost the FinFETs I DS and consequently their abilities to buffer electrical current, aiming the reduction of the number of Fins that must be put in parallel to define a specific I DS and their occupied die areas. (AU) | |
| FAPESP's process: | 20/09375-0 - Design and interactive optimization tool for integrated circuits based on computational intelligence |
| Grantee: | Rodrigo Alves de Lima Moreto |
| Support Opportunities: | Research Grants - Innovative Research in Small Business - PIPE |