Energy-aware design space exploration framework for heterogeneous architectures with FPGAs and GPUs

• Grant number: 16/18937-7
• Support Opportunities: Scholarships in Brazil - Doctorate (Direct)
• Start date: June 01, 2017
• End date: October 31, 2021
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Vanderlei Bonato
• Grantee: Andre Bannwart Perina
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil
• Associated scholarship(s): 18/22289-6 - High-level mapping framework for heterogeneous architectures with FPGAs and GPUs, BE.EP.DD

Abstract

Over many decades, a broad spectrum of digital architectures were developed for solving different types of problems in terms of their characteristics. Some years ago, trends have emerged towards Heterogeneous Computing, where different architectures (e.g. CPUs, GPUs, FPGAs) are used for accelerating large-scale problems. In this method of computation, parts of a source code are separated (usually by wrapping them to functions, known as kernels) to be executed on the heterogeneous accelerators. The task of making such separation efficiently, however, is not trivial. There are many investigations in this area, such as kernel mapping (assigning defined kernels to the cores based on parameters such as data dependency, control flow, etc.), kernel transformation (transforming the code between kernels in order to increase performance, e.g. kernel fusion or fission) among others. Reconfigurable architectures are suitable for heterogeneous computing due to its acceptable performance associated with low energy consumption. In this project, we propose the creation of an integrated design space exploration framework involving mainly GPUs and FPGAs, where kernels mapping and transformations will be applied not only to increase performance but also reducing energy consumption, moving towards the era of green computing. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

PERINA, ANDRE BANNWART; BECKER, JUERGEN; BONATO, VANDERLEI; IEEE. ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. 2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), v. N/A, p. 4-pg., 2019-01-01. (18/22289-6, 16/18937-7)

PERINA, ANDRE BANNWART; BONATO, VANDERLEI; IEEE. Mapping Estimator for OpenCL Heterogeneous Accelerators. 2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018), v. N/A, p. 4-pg., 2018-01-01. (16/18937-7)

PERINA, ANDRE B.; SILITONGA, ARTHUR; BECKER, JURGEN; BONATO, VANDERLEI. ast Resource and Timing Aware Design Optimisation for High-Level Synthesi. IEEE TRANSACTIONS ON COMPUTERS, v. 70, n. 12, p. 2070-2082, DEC 1 2021. (18/22289-6, 16/18937-7)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

PERINA, Andre Bannwart. Lina: a fast design optimisation tool for software-based FPGA programming. 2022. Doctoral Thesis - Universidade de São Paulo (USP). Instituto de Ciências Matemáticas e de Computação (ICMC/SB) São Carlos.