Fabrication and characterization of MOSFET transistors based on ultra-strained silicon nanowires

• Grant number: 22/16809-2
• Support Opportunities: Scholarships in Brazil - Master
• Start date: August 01, 2023
• End date: February 28, 2025
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcos Vinicius Puydinger dos Santos
• Grantee: Kung Shao Chi
• Host Institution: Faculdade de Engenharia Elétrica e de Computação (FEEC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
• Associated research grant(s): 24/12009-7 - 38th Symposium on Microelectronics Technology and Devices - SBMicro 2024, AR.BR

Abstract

Mechanically stressed semiconductors present several physical properties that are of great interest for pure and applied sciences. These features are related to changes in their electrical, thermal and optical properties due to modifications in the material band diagram. Moreover, the fabrication techniques utilized to create stressed structures are of vital importance, as it presents a limiting factor to achieve high stress, stress uniformity, stress type (uniaxial, biaxial, compressive, tensile), as well as the need to use external actuators. In this sense, the enhancement of the electric mobility of carriers in stressed silicon has been widely investigated and applied in the industry of high-performance nanoelectronic devices (transistors), to extend Moore's law.Therefore, in this project it is intended to manufacture nanowires with uniaxial and uniform strain levels well above that used by the industry. This task will be performed in a controlled manner at the nanometer scale, without the use of external mechanical actuators and, with an industry-compatible process to yield an adequate method for transistor fabrication. In addition, the investigation of carrier mobility at very high strain levels is intended to enable a technological breakthrough, thus being a step forward to the fabrication of the next generation high-performance nanowire-based transistors.Furthermore, the stressed nanowires fabricated in this work will be used to study the physical phenomena of giant piezoresistance in nanowires, which has been recently investigated in the literature and has attracted significant attention from the scientific community due to its potential application in high-sensitive sensors and high-performance microelectronics. However, the physical phenomenon behind the giant piezoresistance remains unknown and requires better investigation, which is proposed in this work. It is also intended to fabricate nanowire-based MOSFET devices from highly-strained silicon nanowires using the gate-all-around (GAA) topology for the extraction of the carrier mobility as function of the stress.In summary, we aim to obtain silicon nanowires under variable stress levels for the investigation of the electric mobility of carriers, as well as the giant piezoresistance at mechanical stress levels higher than the values current presented in the literature. This is intended to be achieved with accurate control and without external actuators in a top-down CMOS-compatible technology used in the microelectronics industry.

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

CHI, KUNG SHAO; SPEJO, LUCAS BARROSO; MINAMISAWA, RENATO A.; DOS SANTOS, MARCOS V. PUYDINGER. Single nanofabrication step of low series resistance nanowire-based devices for giant piezoresistance characterization. 2024 38TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO 2024, v. N/A, p. 4-pg., 2024-01-01. (22/16809-2)