Performance evaluation of code optimizations in FPGA accelerators

Author(s)

Gustavo Leite

• Document type: Master's Dissertation
• Press: São José do Rio Preto. 2019-10-11.
• Institution: Universidade Estadual Paulista (Unesp). Instituto de Biociências Letras e Ciências Exatas. São José do Rio Preto
• Defense date: 2019-08-28
• Advisor: Alexandro José Baldassin

Abstract

With the ever increasing power wall in microprocessor design, scientists and engineers shifted their attention to heterogeneous architectures, where in several classes of devices are used for different kinds of computation. Among them are FPGAs whose hardware can be reconfigured after manufacturing. These devices offer comparable performance to CPUs while consuming only a fraction of energy. Infact, the use of FPGAs have been proliferating in recent years and should continue to do so considering the amount of attention these devices are receiving. Still, programmability and performance engineering in FPGAs remain hard. This work presents acompilation of the most prominent code transformations for optimizing code aimed at FPGAs. In this work we also evaluate the performance of programs running on FPGAs. More specifically, we apply a subset of the code transformations to an OpenCL kernel and measure the execution time on a Intel® FPGA. We show that, without applying these transformations before execution, poor performance is observed and the devices are underutilized. (AU)

• FAPESP's process: 17/09065-9 - Scheduling threads and pages on NUMA systems
• Grantee: Gustavo Leite
• Support Opportunities: Scholarships in Brazil - Master