Junctionless nanowire transistors parameters extraction based on drain current measurements

Author(s)

Trevisoli, Renan ^[1] ; Doria, Rodrigo T. ^[2] ; de Souza, Michelly ^[2] ; Barraud, Sylvain ^[3] ; Pavanello, Marcelo A. ^[2]

Affiliation

^[1] Univ Fed ABC, UFABC Santo Andre, Santo Andre - Brazil

^[2] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo - Brazil

^[3] Univ Grenoble Alpes, CEA, LETI, Minatec Campus, F-38054 Grenoble - France

• Document type: Journal article
• Source: Solid-State Electronics; v. 158, p. 37-45, AUG 2019.
• Web of Science Citations: 0

Abstract

The aim of this work is to propose and qualify a systematic method for parameters extraction of Junctionless Nanowire Transistors (JNTs) based on drain current measurements and compact modeling. As junctionless devices present a different conduction mechanism than inversion-mode transistors, the methods developed for the latter devices either are not compatible or cannot be directly applied to JNTs before a deep analysis on their applicability. The current work analyzes the extraction of the series resistance, including a discussion about the influence of the first and second order mobility degradation factors, flatband voltage and low field mobility in junctionless transistors based only on static drain current curves. An analysis of the method accuracy considering the influence of the channel length, nanowire width and height, gate oxide thickness and doping concentration is also presented for devices with different characteristics through three-dimensional numerical simulations. The inclusion of the second order effects in a drain current model is also shown, considering the extracted values. The method applicability is also successfully demonstrated in experimental devices. (AU)

• FAPESP's process: 14/18041-8 - Electrical characterization and modeling of advanced electronic devices
• Grantee: Renan Trevisoli Doria
• Support Opportunities: Scholarships in Brazil - Post-Doctoral