Electrical characterization of stacked SOI nanowires at low temperatures

Author(s)

Rodrigues, Jaime C. C. ; Mariniello, Genaro ; Casse, Mikael ; Barraud, Sylvain ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo A. A.

• Document type: Journal article
• Source: Solid-State Electronics; v. 191, p. 7-pg., 2022-05-01.

Abstract

This work presents the electrical characterization of 2-level vertically stacked nanowire MOSFETs with variable fin widths in the temperature range from 93 K to 400 K. The basic electrical properties, such as threshold voltage, subthreshold slope, and carrier mobility are examined in the linear region with low VDS. In sequence, certain analog figures of merit such as the transconductance, the output conductance, and the voltage gain are assessed in saturation. The threshold voltage variation with temperature is linear and slightly increases for wider devices, which was satisfactorily validated by an analytical model for 3D devices. Additionally, the subthreshold slope remains close to the theoretical limit in the whole range of temperatures. The intrinsic voltage gain is weakly temperature-sensitive in the studied range regardless of the fin width. On the other hand, it increases for narrow devices in all temperatures. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants