Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors

Author(s)

Augusto Ribeiro, Thales ; Cerdeira, Antonio ; Estrada, Magali ; Barraud, Sylvain ; Antonio Pavanello, Marcelo

• Document type: Journal article
• Source: JOURNAL OF COMPUTATIONAL ELECTRONICS; v. 21, n. 3, p. 12-pg., 2022-04-02.

Abstract

This work performs a pragmatic evaluation of the different junctionless devices architectures with channel lengths down to 30 nm on their electrical characteristics. By adopting multiple combinations between the fin height (H-FIN) and the fin width (W-FIN), chosen from the range of published data in the literature, the devices will operate from double-gate (FinFET like) mode towards to nanowire mode. Additionally, junctionless transistors with and without additional doping at the drain and source extensions were studied. Experimentally calibrated 3D TCAD simulations are used to allow for the study of these several combinations. Results show that for long-channel devices the best performance is obtained for tall and narrow fins, leading to the highest on-to-off current ratio (I-ON/I-OFF) and the smallest values of subthreshold swing and DIBL. On the other hand, for short channel devices, independently of the doping level of the extensions, the best results are found for short H-FIN and narrow W-FIN, leading to the smaller values of subthreshold swing and DIBL, with a high I-ON/I-OFF ratio. However, the use of doped extensions degrades the overall device performance of short-channel junctionless devices as will be demonstrated. (AU)

• FAPESP's process: 16/10832-1 - Evaluation and Modeling of Charge Transport in Nanometer MOSFETs for CMOS Circuit Design
• Grantee: Thales Augusto Ribeiro
• Support Opportunities: Scholarships in Brazil - Doctorate
• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants