Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Author(s)

Paz, Bruna Cardoso ; Casse, Mikael ; Barraud, Sylvain ; Reimbold, Gilles ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo Antonio

• Document type: Journal article
• Source: Solid-State Electronics; v. 159, p. 7-pg., 2019-09-01.

Abstract

This work evaluates the operation of p-type Si0.7Ge0.3-On-Insulator (SGOI) nanowires from room temperature down to 5.2 K. Electrical characteristics are shown for long channel devices comparing narrow Omega-gate to quasiplanar MOSFETs (wide fin width). Analysis is performed starting from basic MOSFET electrical parameters extraction, evidence of quantum transport, transconductance and capacitance step-like behavior. Temperature and fin width influence over mobility results are discussed for uniaxial and biaxial compressive strained SGOI. Results are also compared to unstrained p-type SOI nanowires and effective mobility enhancement for SGOI nanowires is still observed for devices with fin width scaled down to 20 nm. Narrow SGOI NW presents mobility improvement over quasi-planar SGOI structure for all temperature range due to beneficial uniaxial strain over biaxial one. Cryogenic operation of nanowires allowed the dissociation of phonon and surface roughness mobility contributions, which are also discussed in this work. Similar phonon-limited mobility contribution dependence on temperature is obtained for both narrow SGOI and unstrained SOI transistors. In order to provide a complete study on the performance of SGOI nanowires, temperature influence is also investigated over analog parameters for narrow SGOI transistor. (AU)

• FAPESP's process: 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors
• Grantee: Bruna Cardoso Paz
• Support Opportunities: Scholarships in Brazil - Doctorate