New method for individual electrical characterization of stacked SOI nanowire MOSFETs

Author(s)

Paz, Bruna Cardoso ; Casse, Mikael ; Barraud, Sylvain ; Reimbold, Gilles ; Vinet, Maud ; Faynot, Olivier ; Pavanello, Marcelo Antonio ; IEEE

• Document type: Journal article
• Source: 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2017-01-01.

Abstract

A new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (V-B) and consists of three basic main steps, accounting for V-B influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom Omega-NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150 degrees C. (AU)

• FAPESP's process: 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors
• Grantee: Bruna Cardoso Paz
• Support Opportunities: Scholarships in Brazil - Doctorate
• FAPESP's process: 16/06301-0 - Electrical characterization and tridimensional simulation of nanowires MOS transistors
• Grantee: Bruna Cardoso Paz
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate