Scheduling threads and pages on NUMA systems

• Grant number: 17/09065-9
• Support Opportunities: Scholarships in Brazil - Master
• Start date: March 01, 2018
• End date: July 02, 2019
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Alexandro José Baldassin
• Grantee: Gustavo Leite
• Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
• Associated scholarship(s): 18/08116-1 - Scheduling threads and pages in NUMA systems, BE.EP.MS

Abstract

Assigning threads and memory pages to nodes of a NUMA architecture in a way that matches the demand for remote data transfers with the available communication bandwidths and memory-controller capacity in the machine can have a significant impact in the execution time of programs. Such assignment typically requires dealing with four simultaneous goals: (a) keep threads close to the memory pages they access; (b) evenly distribute the workload among nodes; (c) maintain memory demand below memory controllers' bandwidth; and (d) reassign threads and pages to follow changes in the memory access pattern of the program. Several independent researchers have directed efforts to solve this problem in the last couple of years, however, a definitive solution is yet to emerge. In that sense, this research project aims to apply machine learning techniques to improve page and thread migration in NUMA systems. The idea is to collect profiling data to guide the machine learning algorithms and improve the performance of a previous system, called PTB. (AU)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

LEITE, Gustavo. Performance evaluation of code optimizations in FPGA accelerators. 2019. Master's Dissertation - Universidade Estadual Paulista (Unesp). Instituto de Biociências Letras e Ciências Exatas. São José do Rio Preto São José do Rio Preto.