| Full text | |
| Author(s): |
Trevisoli, Renan
[1]
;
Doria, Rodrigo Trevisoli
[1]
;
de Souza, Michelly
[1]
;
Barraud, Sylvain
[2]
;
Vinet, Maud
[2]
;
Pavanello, Marcelo Antonio
[1]
Total Authors: 6
|
| Affiliation: | [1] Ctr Univ FEI, BR-09850901 Sao Bernardo Do Campo - Brazil
[2] Commissariat Energie Atom & Energies Alternat, Lab Elect Technol Informat, F-38054 Grenoble - France
Total Affiliations: 2
|
| Document type: | Journal article |
| Source: | IEEE TRANSACTIONS ON ELECTRON DEVICES; v. 63, n. 2, p. 856-863, FEB 2016. |
| Web of Science Citations: | 9 |
| Abstract | |
This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes shortchannel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results. (AU) | |
| FAPESP's process: | 14/18041-8 - Electrical characterization and modeling of advanced electronic devices |
| Grantee: | Renan Trevisoli Doria |
| Support Opportunities: | Scholarships in Brazil - Post-Doctoral |