| Author(s): |
Doria, R. T.
;
Trevisoli, R.
;
de Souza, M.
;
Pavanello, M. A.
;
Flandre, D.
;
IEEE
Total Authors: 6
|
| Document type: | Journal article |
| Source: | 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S); v. N/A, p. 3-pg., 2016-01-01. |
| Abstract | |
This paper aims at demonstrating, for the first time, the use of back bias to improve the analog performance of current mirrors composed by self-cascode structures with 25 nm-long n- and p-type UTBB SOI MOSFETs. The use of back gate bias has shown to enhance the intrinsic gain of p-type devices by about 7 dB, making it higher than the one from a single device with equivalent channel length whereas the mirroring precision has shown to be improved by 20 % with respect to single devices. (AU) | |
| FAPESP's process: | 14/18041-8 - Electrical characterization and modeling of advanced electronic devices |
| Grantee: | Renan Trevisoli Doria |
| Support Opportunities: | Scholarships in Brazil - Post-Doctoral |