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(Reference retrieved automatically from Web of Science through information on FAPESP grant and its corresponding number as mentioned in the publication by the authors.)

Electrical characterization of vertically stacked p-FET SOI nanowires

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Author(s):
Paz, Bruna Cardoso [1] ; Casse, Mikael [2] ; Barraud, Sylvain [2] ; Reimbold, Gilles [2] ; Vinet, Maud [2] ; Faynot, Olivier [2] ; Pavanello, Marcelo Antonio [1]
Total Authors: 7
Affiliation:
[1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo - Brazil
[2] CEA, LETI Minatec, LCTE, Dept Composants Silicium, SCME, Grenoble - France
Total Affiliations: 2
Document type: Journal article
Source: Solid-State Electronics; v. 141, p. 84-91, MAR 2018.
Web of Science Citations: 3
Abstract

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S\&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with {[}1 1 0]- and {[}1 0 0]-oriented channels, as a function of both fin width (W-FIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for {[}1 1 0]-in comparison to {[}1 00]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on I-ON/I-O(FF) by reducing W-FIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for {[}1 1 0]- and {[}1 0 0]-oriented NWs, respectively. (AU)

FAPESP's process: 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors
Grantee:Bruna Cardoso Paz
Support type: Scholarships in Brazil - Doctorate
FAPESP's process: 16/06301-0 - Electrical characterization and tridimensional simulation of nanowires MOS transistors
Grantee:Bruna Cardoso Paz
Support type: Scholarships abroad - Research Internship - Doctorate