On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks

Author(s)

de Souza, Michelly ^[1] ; Doria, Rodrigo T. ^[1] ; Trevisoli, Renan ^[2] ; Barraud, Sylvain ^[3] ; Pavanello, Marcelo A. ^[1]

Affiliation

^[1] Ctr Univ FEI, BR-09850901 Sao Bernardo Do Campo - Brazil

^[2] Univ Fed ABC, UFABC, BR-09210580 Santo Andre, SP - Brazil

^[3] LETI Commissariat Energie Atom & Energies Alterna, F-38054 Grenoble - France

• Document type: Journal article
• Source: IEEE TRANSACTIONS ON NANOTECHNOLOGY; v. 20, p. 234-242, 2021.
• Web of Science Citations: 0

Abstract

In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier. (AU)

• FAPESP's process: 19/15500-5 - Atomistic simulation of nanowire MOSFETs electrical properties
• Grantee: Marcelo Antonio Pavanello
• Support Opportunities: Regular Research Grants
• FAPESP's process: 14/18041-8 - Electrical characterization and modeling of advanced electronic devices
• Grantee: Renan Trevisoli Doria
• Support Opportunities: Scholarships in Brazil - Post-Doctoral