| Full text | |
| Author(s): |
Paz, Bruna Cardoso
[1]
;
Casse, Mikael
[2]
;
Barraud, Sylvain
[2]
;
Reimbold, Gilles
[2]
;
Vinet, Maud
[2]
;
Faynot, Olivier
[2]
;
Pavanello, Marcelo Antonio
[1]
Total Authors: 7
|
| Affiliation: | [1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo - Brazil
[2] CEA LETI Minatec, Dept Composants Silicium SCME LCTE, Grenoble - France
Total Affiliations: 2
|
| Document type: | Journal article |
| Source: | Solid-State Electronics; v. 149, p. 62-70, NOV 2018. |
| Web of Science Citations: | 0 |
| Abstract | |
This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Q-gate level. The proposed methodology is based on experimental measurements of the total drain current (I-DS) varying the back gate bias (V-B), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for V-B influence on mobility. The behavior of non-stacked Omega-gate NWs are also discussed varying V-B through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on V-B for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Omega-gate. The procedure was validated for a wide range of V-B and up to 150 degrees C. Similar temperature dependence of mobility was observed for both Omega-gate and GAA levels. (AU) | |
| FAPESP's process: | 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors |
| Grantee: | Bruna Cardoso Paz |
| Support Opportunities: | Scholarships in Brazil - Doctorate |